AMD Zen 5 "Strix" APU -

Release Date: 2023/08/10

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Hey everyone! Welcome to Today, we're diving into some exciting details about the upcoming AMD Zen5 Based APU.

The next-gen APU, codenamed "Strix," is built on a 4nm Process and features the Big.Little CPU architecture with 4 Performance Cores and 8 Efficiency Cores. Both the P and E cores support hyper-threading. On the P Core and E Core, the L1 Data cache is 48 kb, while the L1 instruction cache is 32kb. Each P Core boasts 1Mb of cache, and with E cores, it looks like there are 4 in a group, sharing 1mb of L2 Cache. This setup is quite similar to Intel's design. Keep in mind, it's still in the ES stage, so there's more to come. We'll keep you posted on any further updates!


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